Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - sdram veril

Search list

[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog

Description: 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.
Platform: | Size: 776192 | Author: 汪旭 | Hits:

[VHDL-FPGA-Verilog] sdram_verilog

Description: 这是使用VERILOG语言，基于MICRON公司的SDRAM开发的SDRAM接口逻辑-verilog This is the use of language, MICRON-based company's development of the SDRAM SDRAM interface logic
Platform: | Size: 414720 | Author: | Hits:

[source in ebook] mt48lc4m32b2

Description: mt48lc4m32b2.v 是128M sdram 中典型设计。。可以借鉴。-mt48lc4m32b2.v 128M sdram is typical design. . Be used.
Platform: | Size: 8192 | Author: chenliang | Hits:

[VHDL-FPGA-Verilog] very-good-ok-ref-ddr-sdram-verilog

Description: Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
Platform: | Size: 894976 | Author: 姚明 | Hits:

[ARM-PowerPC-ColdFire-MIPS] mem_ctrl.tar

Description: verilog 写的 memory controller ，可以控制SDRAM SRAM NOR -written in Verilog memory controller, can control SDRAM SRAM NOR
Platform: | Size: 331776 | Author: youjia | Hits:

[Other] SDRAM-HY57V641620

Description: 动态随即存储器的时序和工作原理，剖析了其运行的状态机，对底层程序开发有帮助（例子是关于HY57V641620）-Then the dynamic memory timing and working principle, analyzes the state machine its running on the bottom of program development helpful (example is the HY57V641620)
Platform: | Size: 432128 | Author: hlc | Hits:

[VHDL-FPGA-Verilog] (fpga)sdram

Description: verilog 代码，读写SDRAM 不带仿真，需要自己编写测试文件-Verilog code, read and write SDRAM simulation without the need to prepare their own test documentation
Platform: | Size: 19935232 | Author: ch | Hits:

[VHDL-FPGA-Verilog] cameralink

Description: 由于目前基于CameraLink接口的各种相机都不能直接显示，因此本文基于Xilinx公司的Spartan 3系列FPGAXC3S1000-6FG456I设计了一套实时显示系统，该系统可以在不通过系统机的情况下，完成对相机CameraLink信号的接收、缓存、读取并显示 系统采用两片SDRAM作为帧缓存，将输入的CameraLink信号转换成帧频为75Hz，分辨率为1 024×768的XGA格式信号，并采用ADV7123JST芯片实现数模转换，将芯片输出的信号送到VGA接口，通过VGA显示器显示出来-As the CameraLink interface is currently based on a variety of cameras can not directly display, this article based on Xilinx' s Spartan 3 series FPGAXC3S1000-6FG456I designed a set of real-time display system, the system can be achieved without machine case through the system to complete the CameraLink cameras signal reception, cache, read and display systems use two SDRAM frame buffer as the input signals into the CameraLink frame rate of 75Hz, a resolution of 1 024 × 768 for XGA format signal, and using ADV7123JST chip digital-analog conversion, the chip output signal to the VGA port, through the VGA display monitor
Platform: | Size: 13312 | Author: lilei | Hits:

[VHDL-FPGA-Verilog] c_xapp851

Description: 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM （JEDEC DDR400 (PC3200) 标准）控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes the Virtex ™ -5 devices to achieve 200 MHz DDR SDRAM (JEDEC DDR400 (PC3200) standard) controller. The Design and Implementation of the use of IDELAY unit to adjust read data timing. Reading the data calibration and adjust the timing for completion of this controller.
Platform: | Size: 408576 | Author: 陈阳 | Hits:

CodeBus www.codebus.net